1. Field of the Invention
The present invention relates to clock generators and more particularly to crystalless, trimmable, low power clocks where temperature, supply voltage and fabrication processes are compensated over operating variables. Herein “trim” refers to the composite of tuning the output frequency itself and the output frequency's sensitivity to temperature, and chip fabrications processes that affect offsets and other known circuits variations.
2. Background Information
Precision crystal clocks are found in many digital systems (e.g., communications, computing, instrumentation) since they produce a frequency that is stable over temperature, the supply voltage and with respect to the processing steps that produce any associated electronics found in such digital systems. A crystal is limited to one frequency, but other frequencies may be produced using phase locked loops and other such related circuitry. However, crystals remain limited in frequencies that may be generated, they are comparatively bulky, costly and must be added to, rather than fabricated with, the integrated circuitry found in modern high density digital electronics. Hence there digital circuit designers are continuing to replace crystal clocks with electronic designs that are fabricated integral (as part of at the same time) with the digital system electronics.
Commonly found clock circuits, not using crystals, include VCO's (Voltage Controlled Oscillators of various types) and ICO's (Current Controlled Oscillators. Delay circuits e.g., inverters, may be arranged in a feedback ring or RC's (Resistor-Capacitor) arranged in a feedback circuit to form an oscillator. The design issues of all such clock circuits include variations that change the designed frequency. These variables include, most prominently, those introduced by: the processes by which the circuits are made; supply voltage changes, and temperature changes. This group of variables is commonly referred to as PVT (Process, Voltage, and Temperature).
It is common to find variations over the PVT ranges that apply to most digital circuits of as much +/−10% or more. Laser trimming may reduce this percentage, but still the variations found in the known art are often unacceptable. U.S. Pat. Nos. 6,191,660 and 6,798,299, assigned to Cypress Semiconductor Corp, of San Jose, Calif. are directed to crystal-less clocks. Both of these patents are hereby incorporated herein by reference. These designs offer trimming of components and functions, e.g., DACs (Digital to Analog Converters), other electronic components (resistors, capacitors, transistors, etc.) and current sources. However, the designs found in these patents consume high power and do not account for power supply variations that affect frequency. Moreover, is these patents disclose trimming to a reference current that is uncontrolled. Such a current is mirrored in such a way as to “overdrive” the clock thus further magnifying power consumption. These patents provide temperature compensate in the oscillator but do not disclose a circuit or method to trim the temperature coefficient of the circuitry generating the clock. Moreover none compensate for post fabrication temperature effects as does an embodiment of the present invention.
The present invention is directed to improving upon the limitations found in the prior art.